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1 fixed gain dual port class-g differential xdsl line driver ISL1561 the ISL1561 is a fixed gain dual port class-g differential amplifier designed for driving full rate adsl2+ and vdsl2 signals at very low power dissipation. the driver runs on a single +14v power supply and internally generates higher supply voltages when needed to enable power efficient operation for high peak-to-average ratio (par) adsl2+ and vdsl2 signals. in adsl2+ mode of operation with full 19.8dbm transmit signal power across 100 line load, each port consumes only 520mw of power, while with 19.5dbm vdsl2 8b profile a port consumes 610mw of power. in vdsl2 17a mode of operation with 14.5dbm transmit power, a port will consume 411mw of power. these typical power consumption figures account for receiver hybrid loading effe cts and transformer losses. the ISL1561 provides two ports of wideband, current feedback amplifiers optimized for low power consumption in xdsl systems. the drivers achieve an average upstream missing band power ratio (mbpr) distortion of better than -64dbc under 19.8dbm transmit signal power into 100 load. a three pin serial interface is used to pr ogram an 8-bit internal register to set each port?s supply current with 0.5ma step size. this flexibility allows the dsp to optimize each port separately during modem training. the device is supplied in a thermally-enhanced small footprint (4mmx4mm) 24 lead qfn package. the ISL1561 is specified for operation over the full -40c to +85c industrial temperature range and is pb-free rohs compliant. features ? internal fixed gain of 11.6v/v to transformer (see figure 3) ? 360ma output drive capability ?41.8v p-p differential output drive into 100 in class g mode ? vdsl2 8b profile mtpr of -64dbc ? vdsl2 17a profile mtpr of -60dbc ? adsl2+, vdsl2 8b and 17a power consumption of 520mw, 610mw and 411mw respectively ? 8-bit programmable register to set supply current on each port ? 3 pin serial port interface applications ? dual port adsl2+ and vdsl2 dslam alternate part ? isl1591 class ab vdsl driver figure 1. block diagram figure 2. class g+ vs class ab driver total power class ab driver power management +14v analog input bias current setting switch signal both ports serial interface afe output of driver supply rails of line drivers sclk sdata boost inp out cpp cpsw cmsw cmm cs 1 of 2 ports 0 100 200 300 400 500 600 700 800 900 2 4 6 8 10 12 14 16 18 20 tx power (dbm) power consumption (mw) 8b class ab 17a class ab 8b class g 17a class g caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. february 26, 2013 fn7941.1
ISL1561 2 fn7941.1 february 26, 2013 pin configuration ISL1561 (24 ld qfn) top view thermal pad 18 17 16 15 14 13 24 23 22 21 20 8 9 10 11 12 1 2 3 4 5 6 inpa inpb vcmab vcmcd inpc inpd vsp cpp cmm cmsw gnd boost sdata fba outa outb sclk fbd outd outc fbc 7 19 cs fbb thermal pad connects to ground cpsw pin descriptions ISL1561 (24 ld qfn) pin name function 1 inpa amplifier a non-inverting input 2 inpb amplifier b non-inverting input 3 vcmab input common mode bias for port ab 4 vcmcd input common mode bias for port cd 5 inpc amplifier c non-inverting input 6 inpd amplifier d non-inverting input 7 cs chip select, low enables data input to logic 8 sclk serial clock input 9 fbd feedback pin for amplifier d 10 outd amplifier d output 11 outc amplifier c output 12 fbc feedback pin for amplifier c 13 gnd ground 14 cmsw internal negative boost supply 15 cmm internal negative supply 16 cpp internal positive supply 17 cpsw internal positive boost supply 18 vsp positive supply voltage 19 fbb feedback pin for amplifier b 20 outb amplifier b output 21 outa amplifier a output 22 fba feedback pin for amplifier a 23 sdata serial data write 24 boost class g control input
ISL1561 3 fn7941.1 february 26, 2013 figure 3. connection diagram 5.1 3.5k r f vsp + - afe 3.5k r f + - r g gnd ? ISL1561 ? ISL1561 5.1 100 line 1:1.4 typical differential i/o line driver (1 of 2 ports) rp rp rc vcm +vsp rc fb fb out out inp inp isp adjust logic spi isp port control output positive supply output negative supply class g control boost control + power control cmsw cmm power control + cpsw cpp 0.1f 0.1f 0.1f 1f 1f 100k 100k 733 1.33k 1.33k 1.78k 1.78k ordering information part number (notes 2, 3) part marking operating ambient temp range (c) package (pb-free) pkg. dwg. # ISL1561irz 15 61irz -40 to +85 24 ld qfn l24.4x4h ISL1561irz-t13 (note 1) 15 61irz -40 to +85 24 ld qfn l24.4x4h notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL1561 . for more information on msl please see tech brief tb363 .
ISL1561 4 fn7941.1 february 26, 2013 absolute maximum ratings (t a = +25 c) thermal information v s + voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v driver v in + voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd to v s + spi and boost pin voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v v cm voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd to v s + current into any input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8ma continuous output current for long term re liability. . . . . . . . . . . . . . . . .50ma esd rating human body model (tested per jesd22-a114f). . . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 300v charge device model (tested per jesd22-c101e). . . . . . . . . . . . . .1.5kv thermal resistance (typical) ja (c/w) jc (c/w) 24 ld qfn package (notes 4, 5) 44 5 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see performance curve storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-40c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +150c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v sp = +14v, r l-diff =51 differential (emulating transformer input load), refer to figure 3, t a = +25c. ports tested separately unless otherwise indicated. parameter description conditions min (note 6) typ max (note 6) unit ac performance av gain across the load, r b = 5.1 11.6 v/v bw -3db bandwidth i s = 14ma/port, v o < 2v pp-diff 110 mhz i s = 10ma/port, v o = 5v pp-diff 70 mhz gain flatness small signal gain flatness i s = 14ma/port, 17.6mhz 0.3 db i s = 14ma/port, 30mhz 0.9 db sr slew rate v out = 16v p-p-diff (20% to 80%) 560 1000 v/s 200khz harmonic distortion 2nd harmonic 10ma/port, v out = 10v p-p-diff -95 dbc 3rd harmonic 10ma/port, v out = 10v p-p-diff -83 dbc thd 10ma/port, v out = 10v p-p-diff -83 dbc 4mhz harmonic distortion 2nd harmonic 10ma/port, v out = 10v p-p-diff -80 dbc 3rd harmonic 10ma/port, v out = 10v p-p-diff -75 dbc thd 10ma/port, v out = 10v p-p-diff -74 dbc mbpr average missing-band power ratio 26khz to 8mhz, 5khz tone spacing, p line = 19.5dbm, vdsl2+ 8b, us1 -64 dbc e o output voltage noise f = 1mhz, differential each port 110 nv/ hz e o-cm common mode output noise at each port pair f = 1mhz 190 nv/ hz control features v high input high voltage sclk, sdata, cs, boost inputs 2.3 v v low input low voltage sclk, sdata, cs, boost inputs 0.8 v i high input high current for pull-up pins cs, boost v in = 3.3v -28 -23 -18 a i high input high current for pull-down pins sclk, sdata v in = 3.3v 40 50 60 a
ISL1561 5 fn7941.1 february 26, 2013 i low input low current for pull-up pins cs, boost v in = 0v -88 -73 -58 a i low input low current for pull-down pins sclk, sdata v in = 0v -0.2 0 +0.2 a supply characteristics v s operating supply voltage +10 +14 +14.7 v v cpp voltage on the cpp pin boost = 0v (class ab) 7 v v cpsw maximum voltage on the cpsw pin boost = 0v (class ab) 14 v v cmm voltage on the cmm pin boost = 0v (class ab) 7 v v cmsw minimum voltage on the cmsw pin boost = 0v (class ab) 0 v i sp positive supply current per port all ou tputs at 0v, boost = 0v, sdata = 8?h7f for registers 3 and 7 17.5 19.5 21.5 ma all outputs at 0v, boost = 0v, sdata = 8?h1c for registers 3 and 7 9.8 10.3 10.8 ma all outputs at 0v, boost = 0v, sdata = 8?h0f for registers 3 and 7 6.8 7.2 7.6 ma i sp (power-down) supply current per port all outputs at 0v, boost = 0v, sdata = 8?h80 for registers 3 and 7 2.0 2.5 3.0 ma output characteristics v out loaded output swing high (single-ended to gnd) r l = 51 , class ab (see figure 3) 11.9 12.4 v loaded output swing high (single-ended to gnd) r l = 51 , class ab (see figure 3) 1.6 2.1 v i ol linear output current r l = 10 , f = 100khz, thd = -60dbc (5 differential) 360 ma v os-dm differential output offset voltage sdata = 8?h1c -125 18 +125 mv v os-cm common mode output offset voltage sdata = 8?h1c (offset from input vcm) 6.85 7.09 mv input characteristics cmir common mode input range at each of the 4 non-inverting input pins class ab +4.5 +9.5 v cmrr dc common mode rejections for each port. v cm = +4.5v to +9.5v v cm to differential mode output (input referred) i sp = 10ma/port 66 db v cm to common mode output (output referred) i sp = 10ma/port 40 db psrr dc power supply rejections for each port to differential output (input referred) +v s = +7v to +14v, gnd = 0v, i sp = 10ma/port 74 db dc power supply rejections for each port to common mode output (output referred) +v s = +7v to +14v, gnd = 0v, i sp = 10ma/port 55 db rin input resistance differential 5.0 6.0 7.1 k digital f clk clock frequency 0.1 10 mhz note: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications v sp = +14v, r l-diff =51 differential (emulating transformer input load), refer to figure 3, t a = +25c. ports tested separately unless othe rwise indicated.(continued) parameter description conditions min (note 6) typ max (note 6) unit
ISL1561 6 fn7941.1 february 26, 2013 typical performance curves v cc = +14v, rb = 5.1 , gain at the load = 11.6v/v (differential), r load = 51 , t a = +25c, unless otherwise noted. figure 4. small signal frequency response vs bias current figure 5. large signal frequency response figure 6. small signal frequency response vs c load figure 7. common mode small signal response vs bias current figure 8. power consumption vs line power figure 9. vdsl2+ 8b avg. mbpr us1 vs line power -9 -6 -3 0 3 6 9 1m 10m 100m 1g frequency (hz) v o = 0.5v p-p normalized gain (db) 8ma/port 10ma/port 12ma/port 14ma/port -9 -6 -3 0 3 6 9 10ma/port 1m 10m 100m 1g frequency (hz) normalized gain (db) v o = 1v p-p v o = 2v p-p v o = 5v p-p v o = 10v p-p -6 -3 0 3 6 9 10ma/port 1m 10m 100m 1g frequency (hz) normalized gain (db) c l = 5.6pf c l = 15pf c l = 27pf c l = 39pf -9 -6 -3 0 3 6 9 100k 1m 10m 100m frequency (hz) v o = 0.5v p-p 8ma/port 10ma/port 12ma/port 14ma/port gain (db) 200 300 400 500 600 700 8 10 12 14 16 18 20 line power (dbm) power consumption (mw) 8mhz profile (10ma/port) 17mhz (12ma/port) adsl2 smartg (8ma/port) 0 100 200 300 400 500 600 700 -80 -75 -70 -65 -60 -55 -50 10 11 12 13 14 15 16 17 18 19 20 cf = 6.56v/v mbpr (dbc) pd (mw) power consumption (mw) mbpr (dbc) line power (dbm)
ISL1561 7 fn7941.1 february 26, 2013 figure 10. harmonic distortion vs frequency figure 11. harmonic distor tion vs bias current figure 12. harmonic vs r load figure 13. harmonic distortion vs output amplitude figure 14. differential output voltage noise f igure 15. common mode output voltage noise typical performance curves v cc = +14v, rb = 5.1 , gain at the load = 11.6v/v (differential), r load = 51 , t a = +25c, unless otherwise noted. (continued) -100 -90 -80 -70 -60 -50 -40 -30 10ma/port v o = 2v p-p frequency (hz) harmonic distortion (dbc) 2nd hd 3rd hd 100k 1m 10m -100 -90 -80 -70 -60 -50 -40 8 10 12 14 16 18 20 bias current(ma) fc = 4mhz v o = 2v p-p harmonic distortion (dbc) 2nd hd 3rd hd -90 -85 -80 -75 -70 -65 -60 25 50 75 100 125 r load ( ) 10ma/port fc = 4mhz v o = 2v p-p 2nd hd 3rd hd harmonic distortion (dbc) -90 -85 -80 -75 -70 -65 -60 -55 -50 1 3 5 7 9 11 13 15 differential output voltage (v p-p ) 10ma/port fc = 4mhz harmonic distortion (dbc) 2nd hd 3rd hd 10 100 1000 frequency (hz) 1k 10k 100k 1m 10m 100m nv/ hz 10 100 1000 10k 100k 1m 10m 100m frequency (hz) nv/ hz
ISL1561 8 fn7941.1 february 26, 2013 figure 16. channel-to-channel crosstalk figure 17. off-isolation figure 18. enable response figure 19. disable response figure 20. quiescent current per port vs codes typical performance curves v cc = +14v, rb = 5.1 , gain at the load = 11.6v/v (differential), r load = 51 , t a = +25c, unless otherwise noted. (continued) -100 -90 -80 -70 -60 -50 -40 -30 -20 10ma/port 100k 1m 10m 100m frequency (hz) gain (db) channel ab -> cd channel cd -> ab -120 -110 -100 -90 -80 -70 -60 10ma/port 100k 1m 10m 100m frequency (hz) gain (db) t en = 600ns outa sdata outa sdata t dis = 1.6s 0 5 10 15 20 25 0 20 40 60 80 100 120 140 iq code iq/port (ma)
ISL1561 9 fn7941.1 february 26, 2013 figure 21. quiescent current vs temperature figure 22. gain at load vs temperature figure 23. slew rate vs temperature figure 24. 4mhz harmonic distortion vs temperature figure 25. output swing vs temperature figure 26. output offset cm and dm vs temperature typical performance curves v cc = +14v, rb = 5.1 , gain at the load = 11.6v/v (differential), r load = 51 , t a = +25c, unless otherwise noted. (continued) 0 5 10 15 20 25 30 35 40 45 -40 -20 0 20 40 60 80 temperature (c) total iq for 2 ports (ma) i q = ?7f? i q = ?1c? 11.40 11.45 11.50 11.55 11.60 11.65 11.70 -40 -20 0 20 40 60 80 temperature (c) gain at load (v/v) gain 900 920 940 960 980 1000 1020 1040 1060 1080 1100 -40 -20 0 20 40 60 80 temperature (c) slew rate (v/s) sr -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -40 -20 0 20 40 60 80 temperature (c) 3rd hd 2nd hd hd (dbc) 10v p-p 0 2 4 6 8 10 12 14 -40 -20 0 20 40 60 80 temperature (c) high swing low swing output swing (v) 0 1 2 3 4 5 6 7 8 -40 -20 0 20 40 60 80 temperature (c) vos (mv) cm dm
ISL1561 10 fn7941.1 february 26, 2013 general description the ISL1561 is a class g amplifier designed to reduce power consumption in adsl2+ and vdsl 2 applications compared to class ab. with the high par us ed for xdsl signals, a supply voltage of +14v can be used for the majority of the small amplitude cycles while boosting to a supply voltage of +28v can be used for the few high amplitude cycles. digital interface a 12-bit serial port interface is used to program ISL1561. the first bit defines the write (1?b1) and read (1?b0) operation to the register. the following 3-bit call s the registers. the last 8-bit programs the registers. default start-up for ISL1561 is in disable mode with boost and cs pins having internal pull ups and sclk and sdata pins having internal pull downs. ISL1561 can only be programmed through the spi when cs is set low. register listing address function bit description 3?h3 setting of quiescent current of port ab [7] boost disable [6:0] program quiescent current of port ab. 3?h7 setting of quiescent current of port cd [7] boost disable [6:0] program quiescent current of port cd. figure 27. 12 bits seri al addressing diagram figure 28. 12 bits serial addressing diagram cs 123 0 z-hi z-hi sclk sdata d[0] addr[0:2] current setting value d[1] d[2] d[3] d[4] d[5] d[6] d[7] w/r bn b(n-1) b(n-2) b1 b0 sclk sdata lsb msb t t sd t hd tt r t w load lsb first, msb last t f cs t sc t hc t sc
ISL1561 11 fn7941.1 february 26, 2013 boost control table 2 summarizes the logic of register ms b on boost operations followed by figure 29 with the recommended look ahead timing f or the boost signal. table 1. serial timing diagram parameter recommended operating range description t 100ns clock period t r /t f 0.05*t clock rise/clock fall t hc 7ns data hold time t sd 10ns data setup time t hc 2.8ns cs hold time t sc 0.5ns cs setup time t w 0.50*t clock pulse width table 2. register msb on boost operation reg3 8?h[7] reg7 8?h[7] boost pin boost operation 0x 1 1 x0 1 1 11 x 0 xx 0 0 note: x = do not care figure 29. serial timing diagram t d boost signal table 3. external boost signal timing parameters parameter recommended operating range description t d 100ns look ahead boost
ISL1561 12 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7941.1 february 26, 2013 for additional products, see www.intersil.com/product_tree about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL1561 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change january 24, 2013 fn7941.1 changed min/max specs for ?differential output offset voltage? on page 5 from -75/75mv to -125/125mv. november 21, 2012 added resistor values to figure 3 on page 3. edited table heading for columns 1 and 2 in table 2 on page 11. october 5, 2012 fn7941.0 initial release.
ISL1561 13 fn7941.1 february 26, 2013 package outline drawing l24.4x4h 24 lead quad flat no-lead plastic package rev 0, 09/11 c0 . 2 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 4.00 (4x) 0.15 6 pin 1 index area 19 pin #1 index area 24 2.50 20x 0.50 exp. dap 6 1 18 12 24x 0.40 0.10 7 6 2.50 see detail "x" seating plane 0.08 0.10 c c c ( 3.80 ) ( 2.50 ) ( 24 x 0.60) (24x .25) ( 20x 0.50) ( 3.80 ) ( 2.50) typical recommended land pattern 0.10 24x 0.25 +0.07 a m c 4 2.50 0.05 sq. 0.25 min (4 sides) -0.05 0.90 0.10 dimensioning and tolerancing conform to amsey14.5m-1994. dimension applies to the metallized terminal and is measured the configuration of the pin #1 identifier is optional, but must be dimensions in ( ) for reference only. between 0.15mm and 0.30mm from the terminal tip. tiebar shown (if present) is a non-functional feature. unless otherwise specified, tolerance : decimal 0.05 4. 5. 6. 3. 2. dimensions are in millimeters. notes: 1. located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 13 compliant to jedec mo-220 vggd-8 7. b bottom view detail "x" side view top view

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